VectorVMRuntime.cpp File Reference

#include "VectorVMRuntime.h"
#include "HAL/IConsoleManager.h"
#include "Math/RandomStream.h"
#include "VectorVM.h"
#include "VectorVMBridge.h"
#include "VectorVMTypes.h"

Classes
struct	VectorVM::Runtime::FVectorVMBatchState

Namespaces
namespace	VectorVM
namespace	VectorVM::Runtime

Macros
#define	VVM_MIN(a, b)   ((a) < (b) ? (a) : (b))
#define	VVM_MAX(a, b)   ((a) > (b) ? (a) : (b))
#define	VVM_CLAMP(v, min, max)   ((v) < (min) ? (min) : ((v) < (max) ? (v) : (max)))
#define	VVM_ALIGN(num, alignment)   (((size_t)(num) + (alignment) - 1) & ~((alignment) - 1))
#define	VVM_ALIGN_4(num)   (((size_t)(num) + 3) & ~3)
#define	VVM_ALIGN_8(num)   (((size_t)(num) + 7) & ~7)
#define	VVM_ALIGN_16(num)   (((size_t)(num) + 15) & ~15)
#define	VVM_ALIGN_32(num)   (((size_t)(num) + 31) & ~31)
#define	VVM_ALIGN_64(num)   (((size_t)(num) + 63) & ~63)
#define	VVM_PTR_ALIGN   VVM_ALIGN_16
#define	VVM_REG_SIZE   sizeof(FVecReg)
#define	VVM_CHUNK_FIXED_OVERHEAD_SIZE   512
#define	VVMSet_m128Const(Name, V)   static const MS_ALIGN(16) float VVMConstVec4_##Name##4[4] GCC_ALIGN(16) = { V, V, V, V }
#define	VVMSet_m128Const4(Name, V0, V1, V2, V3)   static const MS_ALIGN(16) float VVMConstVec4_##Name##4[4] GCC_ALIGN(16) = { V0, V1, V2, V3 }
#define	VVMSet_m128iConst(Name, V)   static const MS_ALIGN(16) uint32 VVMConstVec4_##Name##4i[4] GCC_ALIGN(16) = { V, V, V, V }
#define	VVMSet_m128iConst4(Name, V0, V1, V2, V3)   static const MS_ALIGN(16) uint32 VVMConstVec4_##Name##4i[4] GCC_ALIGN(16) = { V0, V1, V2, V3 } /* equiv to setr */
#define	VVM_m128Const(Name)   (*(VectorRegister4f *)&(VVMConstVec4_##Name##4))
#define	VVM_m128iConst(Name)   (*(VectorRegister4i *)&(VVMConstVec4_##Name##4i))
#define	VVMDebugBreakIf(expr)   if ((expr)) { PLATFORM_BREAK(); }
#define	VVM_OUTPUT_FUNCTION_HEADER(CT_InputInsOutputTypeOpCode)
#define	VVM_OUTPUT_FUNCTION_FOOTER   return InsPtr
#define	VVM_NULL_FN_ARGS   const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, int NumLoops
#define	VVM_Dispatch_execFn0done_0done(...)   NULL; goto done_loop;
#define	VVM_OP_START   switch ((EVectorVMOp)InsPtr[-1])
#define	VVM_OP_CASE(op)   case EVectorVMOp::op:
#define	VVM_OP_NEXT   break
#define	VVM_OP_XM(OpCode, Cat, NumInputs, NumOutputs, Type, ...)   VVM_OP_CASE(OpCode) InsPtr = VVM_Dispatch_execFn##NumInputs##Type##_##NumOutputs##Type(CT_MultipleLoops, InsPtr, BatchState, ExecCtx, VVM_Exec##NumInputs##Type##_##OpCode, NumLoops); VVM_OP_NEXT;
#define	VVM_OP_XM(OpCode, Cat, NumInputs, NumOutputs, Type, ...)   VVM_OP_CASE(OpCode) InsPtr = VVM_Dispatch_execFn##NumInputs##Type##_##NumOutputs##Type(CT_MultipleLoops, InsPtr, BatchState, ExecCtx, VVM_Exec##NumInputs##Type##_##OpCode, NumLoops); VVM_OP_NEXT;

Typedefs
typedef const uint8 *()	VectorVM::Runtime::VVMFn_null(VVM_NULL_FN_ARGS)
typedef VectorRegister4f()	VectorVM::Runtime::VVMFn_1f(FVectorVMBatchState *, VectorRegister4f a)
typedef VectorRegister4f()	VectorVM::Runtime::VVMFn_2f(FVectorVMBatchState *, VectorRegister4f a, VectorRegister4f b)
typedef VectorRegister4f()	VectorVM::Runtime::VVMFn_3f(FVectorVMBatchState *, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
typedef VectorRegister4f()	VectorVM::Runtime::VVMFn_4f(FVectorVMBatchState *, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
typedef VectorRegister4f()	VectorVM::Runtime::VVMFn_5f(FVectorVMBatchState *, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d, VectorRegister4f e)
typedef VectorRegister4i()	VectorVM::Runtime::VVMFn_1i(FVectorVMBatchState *, VectorRegister4i a)
typedef VectorRegister4i()	VectorVM::Runtime::VVMFn_2i(FVectorVMBatchState *, VectorRegister4i a, VectorRegister4i b)
typedef VectorRegister4i()	VectorVM::Runtime::VVMFn_3i(FVectorVMBatchState *, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)

Functions
void *	VectorVM::Runtime::VVMDefaultRealloc (void *Ptr, size_t NumBytes, const char *Filename, int LineNumber)
void	VectorVM::Runtime::VVMDefaultFree (void *Ptr, const char *Filename, int LineNumber)
	VectorVM::Runtime::VVMSet_m128Const (One, 1.f)
	VectorVM::Runtime::VVMSet_m128Const (NegativeOne, -1.f)
	VectorVM::Runtime::VVMSet_m128Const (OneHalf, 0.5f)
	VectorVM::Runtime::VVMSet_m128Const (Epsilon, 1.e-8f)
	VectorVM::Runtime::VVMSet_m128Const (HalfPi, 3.14159265359f *0.5f)
	VectorVM::Runtime::VVMSet_m128Const (QuarterPi, 3.14159265359f *0.25f)
	VectorVM::Runtime::VVMSet_m128Const (FastSinA, 7.5894663844f)
	VectorVM::Runtime::VVMSet_m128Const (FastSinB, 1.6338434578f)
	VectorVM::Runtime::VVMSet_m128Const (Log2, 0.6931471806f)
	VectorVM::Runtime::VVMSet_m128Const (OneOverLog2, 1.4426950409f)
	VectorVM::Runtime::VVMSet_m128iConst (FMask, 0xFFFFFFFF)
	VectorVM::Runtime::VVMSet_m128iConst4 (ZeroOneTwoThree, 0, 1, 2, 3)
	VectorVM::Runtime::VVMSet_m128iConst4 (ZeroTwoFourSix, 0, 2, 4, 6)
	VectorVM::Runtime::VVMSet_m128Const4 (ZeroOneTwoThree, 0.f, 1.f, 2.f, 3.f)
	VectorVM::Runtime::VVMSet_m128iConst (RegOffsetMask, 0x7FFF)
	VectorVM::Runtime::VVMSet_m128Const (RegOneOverTwoPi, 1.f/2.f/3.14159265359f)
	VectorVM::Runtime::VVMSet_m128iConst (AlmostTwoBits, 0x3fffffff)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVMf2i (VectorRegister4i v0)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVMi2f (VectorRegister4f v0)
VM_FORCEINLINE uint16	VectorVM::Runtime::float_to_half_fast3_rtne (uint32 f_in)
void	VectorVM::Runtime::VVMMemCpy (void *dst, void *src, size_t bytes)
void	VectorVM::Runtime::VVMMemSet32 (void *dst, uint32 val, size_t num_vals)
void	VectorVM::Runtime::VVMMemSet16 (void *dst, uint16 val, size_t num_vals)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_exec_index (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_exec_indexf (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_exec_index_addi (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, int NumLoops)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_nextRandom (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_half_to_float (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, int NumLoops)
const uint8 *	VectorVM::Runtime::VVM_external_func_call (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn0null_0null (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_null fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn1null_0null (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_null fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn1null_1null (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_null fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn1null_2null (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_null fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn2null_1null (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_null fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn1f_1f (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_1f fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn2f_1f (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_2f fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn3f_1f (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_3f fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn4f_1f (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_4f fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn5f_1f (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_5f fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn2f_2f (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_2f fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn1i_1i (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_1i fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn2i_1i (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_2i fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn3i_1i (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_3i fn, int NumLoops)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Dispatch_execFn1i_2i (const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, VVMFn_1i fn, int NumLoops)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_add (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_sub (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_mul (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_div (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_mad (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_lerp (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_rcp (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_rsq (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_sqrt (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_neg (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_abs (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_exp (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_exp2 (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_log (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_log2 (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_sin (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_cos (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_tan (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_acos (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_asin (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_atan (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_atan2 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_ceil (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_floor (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_fmod (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_frac (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_trunc (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_clamp (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_min (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_max (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_pow (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_round (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_sign (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_step (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_random (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_noise (VVM_NULL_FN_ARGS)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_cmplt (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_cmple (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_cmpgt (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_cmpge (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_cmpeq (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_cmpneq (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_select (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_addi (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_subi (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_muli (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_divi (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_clampi (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_mini (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_maxi (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec1i_absi (FVectorVMBatchState *BatchState, VectorRegister4i a)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec1i_negi (FVectorVMBatchState *BatchState, VectorRegister4i a)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec1i_signi (FVectorVMBatchState *BatchState, VectorRegister4i a)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_randomi (VVM_NULL_FN_ARGS)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_cmplti (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_cmplei (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_cmpgti (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_cmpgei (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_cmpeqi (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_cmpneqi (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_bit_and (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_bit_or (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_bit_xor (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec1i_bit_not (FVectorVMBatchState *BatchState, VectorRegister4i a)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_bit_lshift (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_bit_rshift (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_logic_and (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_logic_or (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_logic_xor (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec1i_logic_not (FVectorVMBatchState *BatchState, VectorRegister4i a)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec1i_f2i (FVectorVMBatchState *BatchState, VectorRegister4i a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_i2f (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_f2b (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec1f_b2f (FVectorVMBatchState *BatchState, VectorRegister4f a)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec1i_i2b (FVectorVMBatchState *BatchState, VectorRegister4i a)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec1i_b2i (FVectorVMBatchState *BatchState, VectorRegister4i a)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_outputdata_float (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_outputdata_int32 (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_outputdata_half (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_acquireindex (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_external_func_call (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_exec_index (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_noise2D (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_noise3D (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_enter_stat_scope (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_exit_stat_scope (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_update_id (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_acquire_id (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_half_to_float (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_fasi (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_iasf (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_exec_indexf (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_exec_index_addi (VVM_NULL_FN_ARGS)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_cmplt_select (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_cmple_select (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_cmpeq_select (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_cmplti_select (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_cmplei_select (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_cmpeqi_select (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmplt_logic_and (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmple_logic_and (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmpgt_logic_and (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmpge_logic_and (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmpeq_logic_and (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmpne_logic_and (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmplti_logic_and (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmplei_logic_and (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmpgti_logic_and (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmpgei_logic_and (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmpeqi_logic_and (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmpnei_logic_and (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmplt_logic_or (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmple_logic_or (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmpgt_logic_or (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmpge_logic_or (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmpeq_logic_or (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_cmpne_logic_or (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmplti_logic_or (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmplei_logic_or (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmpgti_logic_or (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmpgei_logic_or (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmpeqi_logic_or (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_cmpnei_logic_or (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_mad_add (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_mad_sub0 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_mad_sub1 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_mad_mul (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_mad_sqrt (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec5f_mad_mad0 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d, VectorRegister4f e)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec5f_mad_mad1 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d, VectorRegister4f e)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_mul_mad0 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_mul_mad1 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_mul_add (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_mul_sub0 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_mul_sub1 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_mul_mul (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_mul_max (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_mul_2x (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_add_mad1 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_add_add (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_sub_cmplt1 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_sub_neg (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_sub_mul (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_div_mad0 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_div_f2i (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_div_mul (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_muli_addi (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_addi_bit_rshift (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_addi_muli (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec1i_b2i_2x (FVectorVMBatchState *BatchState, VectorRegister4i a)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_i2f_div0 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_i2f_div1 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_i2f_mul (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_i2f_mad0 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_i2f_mad1 (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_f2i_select1 (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_f2i_maxi (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_f2i_addi (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec3f_fmod_add (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_bit_and_i2f (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_bit_rshift_bit_and (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec2f_neg_cmplt (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_bit_or_muli (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec3i_bit_lshift_bit_or (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b, VectorRegister4i c)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec2null_random_add (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_random_2x (VVM_NULL_FN_ARGS)
VM_FORCEINLINE VectorRegister4i	VectorVM::Runtime::VVM_Exec2i_max_f2i (FVectorVMBatchState *BatchState, VectorRegister4i a, VectorRegister4i b)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_select_mul (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE VectorRegister4f	VectorVM::Runtime::VVM_Exec4f_select_add (FVectorVMBatchState *BatchState, VectorRegister4f a, VectorRegister4f b, VectorRegister4f c, VectorRegister4f d)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec1null_sin_cos (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_inputdata_float (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_inputdata_int32 (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_inputdata_half (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_inputdata_noadvance_float (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_inputdata_noadvance_int32 (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_inputdata_noadvance_half (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_outputdata_float_from_half (VVM_NULL_FN_ARGS)
VM_FORCEINLINE const uint8 *	VectorVM::Runtime::VVM_Exec0null_outputdata_half_from_half (VVM_NULL_FN_ARGS)
void	VectorVM::Runtime::ExecVectorVMState (FVectorVMExecContext *ExecCtx)
FVectorVMState *	VectorVM::Runtime::AllocVectorVMState (TConstArrayView< uint8 > ContextData)
void	VectorVM::Runtime::FreeVectorVMState (FVectorVMState *VVMState)

Macro Definition Documentation

VVM_ALIGN

#define VVM_ALIGN	(		num,
			alignment
	)		(((size_t)(num) + (alignment) - 1) & ~((alignment) - 1))

VVM_ALIGN_16

#define VVM_ALIGN_16

(

num

)

(((size_t)(num) + 15) & ~15)

VVM_ALIGN_32

#define VVM_ALIGN_32

(

num

)

(((size_t)(num) + 31) & ~31)

VVM_ALIGN_4

#define VVM_ALIGN_4

(

num

)

(((size_t)(num) + 3) & ~3)

VVM_ALIGN_64

#define VVM_ALIGN_64

(

num

)

(((size_t)(num) + 63) & ~63)

VVM_ALIGN_8

#define VVM_ALIGN_8

(

num

)

(((size_t)(num) + 7) & ~7)

VVM_CHUNK_FIXED_OVERHEAD_SIZE

#define VVM_CHUNK_FIXED_OVERHEAD_SIZE   512

VVM_CLAMP

#define VVM_CLAMP	(		v,
			min,
			max
	)		((v) < (min) ? (min) : ((v) < (max) ? (v) : (max)))

VVM_Dispatch_execFn0done_0done

#define VVM_Dispatch_execFn0done_0done

(

...

)

NULL; goto done_loop;

VVM_m128Const

#define VVM_m128Const

(

Name

)

(*(VectorRegister4f *)&(VVMConstVec4_##Name##4))

VVM_m128iConst

#define VVM_m128iConst

(

Name

)

(*(VectorRegister4i *)&(VVMConstVec4_##Name##4i))

VVM_MAX

#define VVM_MAX	(		a,
			b
	)		((a) > (b) ? (a) : (b))

VVM_MIN

#define VVM_MIN	(		a,
			b
	)		((a) < (b) ? (a) : (b))

VVM_NULL_FN_ARGS

#define VVM_NULL_FN_ARGS   const bool CT_MultipleLoops, const uint8 *InsPtr, FVectorVMBatchState *BatchState, FVectorVMExecContext *ExecCtx, int NumLoops

VVM_OP_CASE

#define VVM_OP_CASE

(

op

)

case EVectorVMOp::op:

VVM_OP_NEXT

#define VVM_OP_NEXT   break

VVM_OP_START

#define VVM_OP_START   switch ((EVectorVMOp)InsPtr[-1])

VVM_OP_XM [1/2]

#define VVM_OP_XM	(		OpCode,
			Cat,
			NumInputs,
			NumOutputs,
			Type,
			...
	)		VVM_OP_CASE(OpCode) InsPtr = VVM_Dispatch_execFn##NumInputs##Type##_##NumOutputs##Type(CT_MultipleLoops, InsPtr, BatchState, ExecCtx, VVM_Exec##NumInputs##Type##_##OpCode, NumLoops); VVM_OP_NEXT;

VVM_OP_XM [2/2]

#define VVM_OP_XM	(		OpCode,
			Cat,
			NumInputs,
			NumOutputs,
			Type,
			...
	)		VVM_OP_CASE(OpCode) InsPtr = VVM_Dispatch_execFn##NumInputs##Type##_##NumOutputs##Type(CT_MultipleLoops, InsPtr, BatchState, ExecCtx, VVM_Exec##NumInputs##Type##_##OpCode, NumLoops); VVM_OP_NEXT;

VVM_OUTPUT_FUNCTION_FOOTER

#define VVM_OUTPUT_FUNCTION_FOOTER   return InsPtr

VVM_OUTPUT_FUNCTION_HEADER

#define VVM_OUTPUT_FUNCTION_HEADER

(

CT_InputInsOutputTypeOpCode

)

Value:

    uint32 *NumOutputPerDataSet         = BatchState->ChunkLocalData.NumOutputPerDataSet;                    \
    uint32 *StartingOutputIdxPerDataSet = BatchState->ChunkLocalData.StartingOutputIdxPerDataSet;            \
    uint8 **RegPtrTable                 = BatchState->RegPtrTable;                                           \
    uint8 *RegIncTable                  = BatchState->RegIncTable;                                           \
    uint8 **OutputMaskIdx               = BatchState->ChunkLocalData.OutputMaskIdx;                          \
    TArrayView<FDataSetMeta> DataSets   = ExecCtx->DataSets;                                                 \
    uint8  RegType            = (uint8)(CT_InputInsOutputTypeOpCode) - (uint8)EVectorVMOp::outputdata_float; \
    int NumOutputLoops        = InsPtr[0];                                                                   \
    uint8 DataSetIdx          = InsPtr[1];                                                                   \
    uint32 NumOutputInstances = NumOutputPerDataSet[DataSetIdx];                                             \
    uint32 RegTypeOffset      = DataSets[DataSetIdx].OutputRegisterTypeOffsets[RegType];                     \
    const uint16 * RESTRICT SrcIndices       = (uint16 *)(InsPtr + 2);                                       \
    const uint16 * RESTRICT DstIndices       = SrcIndices + NumOutputLoops;                                  \
    InsPtr += 3 + 4 * NumOutputLoops;

VVM_PTR_ALIGN

#define VVM_PTR_ALIGN   VVM_ALIGN_16

VVM_REG_SIZE

#define VVM_REG_SIZE   sizeof(FVecReg)

VVMDebugBreakIf

#define VVMDebugBreakIf

(

expr

)

if ((expr)) { PLATFORM_BREAK(); }

VVMSet_m128Const

#define VVMSet_m128Const	(		Name,
			V
	)		static const MS_ALIGN(16) float VVMConstVec4_##Name##4[4] GCC_ALIGN(16) = { V, V, V, V }

VVMSet_m128Const4

#define VVMSet_m128Const4	(		Name,
			V0,
			V1,
			V2,
			V3
	)		static const MS_ALIGN(16) float VVMConstVec4_##Name##4[4] GCC_ALIGN(16) = { V0, V1, V2, V3 }

VVMSet_m128iConst

#define VVMSet_m128iConst	(		Name,
			V
	)		static const MS_ALIGN(16) uint32 VVMConstVec4_##Name##4i[4] GCC_ALIGN(16) = { V, V, V, V }

VVMSet_m128iConst4

#define VVMSet_m128iConst4	(		Name,
			V0,
			V1,
			V2,
			V3
	)		static const MS_ALIGN(16) uint32 VVMConstVec4_##Name##4i[4] GCC_ALIGN(16) = { V0, V1, V2, V3 } /* equiv to setr */